library ieee;

use ieee.std_logic_1164.all;

-- Start to code on the 23rd of December

entity regfile is port(

	ra1: in std_logic_vector(4 downto 0);
	ra2: in std_logic_vector(4 downto 0);
	wa: in std_logic_vector (4 downto 0);
	wd: in std_logic_vector(31 downto 0);
	regread: in std_logic;
	regwrite: in std_logic;
	rd1: out std_logic_vector(31 downto 0);
	rd2: out std_logic_vector(31 downto 0)

); end entity;





architecture bregfile of regfile is
--type word is array (31 downto 0) of std_logic;
type regmem is array (31 downto 0) of std_logic_vector(31 downto 0);
signal regmem1: regmem;


begin



process(regread,regwrite)
variable a,b,c: integer := 0;
begin


case wa is
when "00000" => a:=0;
when "00001" => a:=1;
when "00010" => a:=2;
when "00011" => a:=3;
when "00100" => a:=4;
when "00101" => a:=5;
when "00110" => a:=6;
when "00111" => a:=7;
when "01000" => a:=8;
when "01001" => a:=9;
when "01010" => a:=10;
when "01011" => a:=11;
when "01100" => a:=12;
when "01101" => a:=13;
when "01110" => a:=14;
when "01111" => a:=15;
when "10000" => a:=16;
when "10001" => a:=17;
when "10010" => a:=18;
when "10011" => a:=19;
when "10100" => a:=20;
when "10101" => a:=21;
when "10110" => a:=22;
when "10111" => a:=23;
when "11000" => a:=24;
when "11001" => a:=25;
when "11010" => a:=26;
when "11011" => a:=27;
when "11100" => a:=28;
when "11101" => a:=29;
when "11110" => a:=30; 
when "11111" => a:=31;
when others => a:=0;
end case;
case ra1 is
when "00000" => b:=0;
when "00001" => b:=1;
when "00010" => b:=2;
when "00011" => b:=3;
when "00100" => b:=4;
when "00101" => b:=5;
when "00110" => b:=6;
when "00111" => b:=7;
when "01000" => b:=8;
when "01001" => b:=9;
when "01010" => b:=10;
when "01011" => b:=11;
when "01100" => b:=12;
when "01101" => b:=13;
when "01110" => b:=14;
when "01111" => b:=15;
when "10000" => b:=16;
when "10001" => b:=17;
when "10010" => b:=18;
when "10011" => b:=19;
when "10100" => b:=20;
when "10101" => b:=21;
when "10110" => b:=22;
when "10111" => b:=23;
when "11000" => b:=24;
when "11001" => b:=25;
when "11010" => b:=26;
when "11011" => b:=27;
when "11100" => b:=28;
when "11101" => b:=29;
when "11110" => b:=30; 
when "11111" => b:=31;
when others => b:=0;
end case;
case ra2 is
when "00000" => c:=0;
when "00001" => c:=1;
when "00010" => c:=2;
when "00011" => c:=3;
when "00100" => c:=4;
when "00101" => c:=5;
when "00110" => c:=6;
when "00111" => c:=7;
when "01000" => c:=8;
when "01001" => c:=9;
when "01010" => c:=10;
when "01011" => c:=11;
when "01100" => c:=12;
when "01101" => c:=13;
when "01110" => c:=14;
when "01111" => c:=15;
when "10000" => c:=16;
when "10001" => c:=17;
when "10010" => c:=18;
when "10011" => c:=19;
when "10100" => c:=20;
when "10101" => c:=21;
when "10110" => c:=22;
when "10111" => c:=23;
when "11000" => c:=24;
when "11001" => c:=25;
when "11010" => c:=26;
when "11011" => c:=27;
when "11100" => c:=28;
when "11101" => c:=29;
when "11110" => c:=30; 
when "11111" => c:=31;
when others => c:=0;
end case;


-- write operation
if (regwrite'event and regwrite='1') then regmem1(a)<=wd ;end if;
--read operation
if (regread'event and regread='1') then rd1<=regmem1(b) ;rd2<=regmem1(c); end if;



end process;

end architecture;

